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Construing the Construction: Federal Circuit Chips Away at IPR Win

Addressing claim construction issues in inter partes review (IPR) proceedings before the Patent Trial & Appeal Board (Board), the US Court of Appeals for the Federal Circuit affirmed an obviousness finding as to some claims but reversed and remanded an obviousness finding as to another claim because of a claim construction error. VLSI Technology LLC v. Intel Corporation, Case Nos. 21-1826, -1827, -1828 (Fed. Cir. Nov. 15, 2022) (Chen, Bryson, Hughes, JJ.)

VLSI owns a patent directed to a technique for alleviating the problems of defects caused by stress applied to bond pads of an integrated circuit. Bond pads are a portion of an integrated circuit that sit above interconnected circuit layers and are used to attach the chip to another electronic component, such as a computer or motherboard. When a chip is attached to another electronic component, forces are exerted on the chip’s bond pad, which can result in damage to the interconnect layers. The patent discloses improvements to the structures of an integrated circuit that reduce the potential for damage to the interconnect layers when the chip is attached to another electronic component while also permitting each of the layers underlying the pad to be functionally independent in the circuit.

VLSI filed suit against Intel alleging infringement of the patent. During claim construction, the district court construed the claim term “force region” to mean a “region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is performed.” Before the district court’s construction but after the suit was filed, Intel filed petitions for IPR of the patent and advocated in its petitions for the same construction of “force region” that the district court ultimately adopted.

VLSI did not contest Intel’s construction, but it later became apparent that the two parties disagreed over the meaning of “die attach,” which formed part of the construction. Intel argued that the term “die attach” refers to any method of attaching a chip to another electronic component, including a method known as wire bonding, which was taught by a prior art reference included in Intel’s petitions. VLSI argued that the term refers to a method of attachment known as “flip chip” bonding and does not include wire bonding. In the Board’s final written decisions, it did not address the term “die attach,” but found that “force region” was not limited to flip chip bonding and subsequently found the challenged claims invalid as obvious. The Board also construed a second disputed term “used for electrical interconnection not directly connected to the bond pad,” which is recited in only one claim of the patent, in favor of Intel, and subsequently found that claim unpatentable. VLSI appealed.

On appeal, VLSI raised a number of procedural and substantive challenges to the Board’s construction of the two disputed terms. VLSI argued that the Board failed to acknowledge and give appropriate weight to the district court’s construction of “force region.” The Federal Circuit dismissed this argument, as there was ample evidence in the record that the Board was aware of and considered the district court’s construction. Additionally, the Court noted that the Board’s construction is consistent with the district court’s construction, specifically explaining that the Board was asked to rule on a separate issue that was not in front of the district court—whether “die attach” includes wire bonding—and the Board’s conclusion was not at odds with the ruling of the district court.

On the merits, the Federal Circuit agreed that the term “force region” is not limited to flip chip bonding. In particular, the Court noted that flip chip bonding is disclosed in a preferred embodiment of the patent, but claims should not be limited to preferred embodiments or specific examples. The Court also found that other embodiments described in the patent adequately disclose wire bonding. Accordingly, the Court affirmed the Board’s finding with respect to the “force region” construction and the ultimate finding of unpatentability as to some claims.

Regarding the “used for electrical interconnection not directly connected to the bond pad” term, the Federal Circuit found that the Board’s construction was too broad and reversed the Board’s holding. In particular, the Court found support for VLSI’s proposed construction in both the specification and amendments made to the claim during prosecution of the patent. Accordingly, the Court reversed and remanded for a determination on that claim based on its construction.

Practice Note: In its challenges to the Board’s construction of “force region,” VLSI also argued that Intel should be estopped from advocating for the Board’s adopted construction because the two parties agree upon the construction for the particular term. The Federal Circuit noted that, while VLSI did not object to Intel’s proposed construction, it was clear that the parties did not agree on the meaning of the term given the dispute over the “die attach” component of the construction. The Court relied on this dispute in denying VLSI’s argument that Intel is estopped. This holding suggests that VLSI’s proposed estoppel may only be effective upon an affirmative agreement between the parties as to the meaning of a claim term, rather than a mere failure to object to a particular construction advanced by the other party.

© 2023 McDermott Will & EmeryNational Law Review, Volume XII, Number 333
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About this Author

Thomas DaMario, Associate, Chicago, intellectual property lawyer, litigation, Illinois, patent litigation, patent prosecution
Associate

Thomas DaMario focuses his practice on intellectual property litigation and patent prosecution.

A licensed professional engineer, Thomas spent several years working for a leading standards organization, helping to develop industry standards related to cybersecurity, cryptography, and access control and intrusion detection systems.

While in law school, Thomas was a staff writer for the Journal of Art, Technology and Intellectual Property and was a participant in the 2016 AIPLA Giles Sutherland Rich Moot Court...

312-984-7527
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